1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a semiconductor device which has a stacked structure of semiconductor encapsulated packages to realize high-density mounting of semiconductor integrated circuit devices. Herein, it is to be noted in the instant specification that the term “semiconductor package” often means a semiconductor device which encapsulates semiconductor integrated circuit device or devices.
2. Description of the Related Art
The inventor has studied, for example, the following technologies for such a semiconductor package.
As generations of large scale integrated circuits (LSIs) of the semiconductor device have been advanced, it has become increasingly difficult to design an integrated circuit of a low power noise. This is attributed to an increase in power noise, which results from increases in consumed current amount and high speed of a semiconductor element for high-speed processing function. In addition, a reduction in noise margin is also caused to occur due to a reduction in source voltage accompanying the progress in the semiconductor process.
Meanwhile, in recent years, a reduction in size and an increase in functionality of electronic devices typified by a cellular phone have been advanced, and there is an increased demand for a stacked semiconductor package with a three-dimensional arrangement in which a memory and a controller LSI are encapsulated in a single package (PKG). In this kind of packaged or encapsulated product, LSIs to which a current is to be supplied (or which consume current) are increased in number. In spite of the fact, a number of solder balls (ball grid array balls, hereinafter, abbreviated as BGA balls) for electrically connecting a printed circuit board (hereinafter, abbreviated as PCB) and the package remains substantially unchanged, and hence the power noise becomes more problematic than before. In particular, the problem becomes apparent in an LSI located in an upper layer of the stack, which is electrically distant from the PCB.
To address the above-mentioned problem, for example, Japanese Unexamined Patent Application Publication (JP-A) No. 2006-295136 proposes a package on package (PoP) structure in which packages are stacked three-dimensionally so that an area of a PoP package provided on an upper side (hereinafter, abbreviated as upper PoP package) is larger than an area of a PoP package provided on a lower side (hereinafter, abbreviated as lower PoP package). In this event, BGA balls for directly supplying current from a PCB are arranged on a periphery of the upper PoP package. This arrangement makes it possible to realize an increase in power supply property to an LSI on the upper PoP package.
One kind of the power noise addressed herein is simultaneous switching noise (hereinafter, abbreviated as SSN) generated when a large number of I/O circuits of the LSI are switched simultaneously. The SSN includes off-chip SSN generated when potential variation occurs due to a current for transferring signals between chips. The off-chip SSN is generated when a transient current is caused to flow in a loop of a power (or ground) wiring and a signal wiring, which connects a driver and a receiver. A voltage value of the noise is determined as a product of a transient current component di/dt, and effective loop inductance (effective inductance: Leff) between the power (ground) wiring and the signal wiring. Therefore, a general method for suppressing the noise involves designing the wirings so that the effective inductance is minimized in the LSI package (PKG) and the PCB. Specifically, the signal wiring and the power/ground wiring are designed to be as close as possible to each other inside the PKG and the PCB, to thereby reduce a loop area of a current path.
Incidentally, the inventor has studied the stacked package semiconductor device as described above to find the following fact.
That is, the power wiring to the LSI mounted on the upper PoP package and the power wiring to the LSI mounted on the lower PoP package are independent to each other inside the lower PoP package. This results in an increased loop area of the current path formed by the power wiring and the signal wiring for transmitting signals between the upper PoP package and the lower PoP package, to thereby significantly increase the above-mentioned off-chip SSN.
Herein, although no detailed analysis has thus far been made about such an off-chip SSN, the off-chip SSN will be described by simply and temporarily referring to an example of a PoP system illustrated in FIGS. 2 and 3 for convenience of description.
The illustrated PoP system has memories (DRAM or flash) 5-1 and 5-2 mounted on an upper PoP 2, and a microcomputer 6 which has a memory controller function and which is mounted on a lower PoP 3. With this structure, signal wirings for transferring signals between memory controller LSIs and the other elements are wired only within the PoP package. In this case, the signal wirings are wired on both the upper PoP 2 and the lower PoP 3 so that the LSIs are connected to each other via a shortest path. In the example illustrated in FIG. 2, current paths are structured by a current path 13 (shown by a dotted line) for signals and a current path 14 (also shown by a dotted line) to a power supply system. Herein, the current path 14 which serves as a return path for the signal current is given from the PCB 1 to the upper PoP2 and the lower PoP3 independently. As a result, a loop area formed by the paths 13 and 14 is increased, which leads to an increase in effective inductance, and hence to an increase in noise. This is expressed as an equivalent circuit illustrated in a schematic diagram of FIG. 3.